1. Field
The present embodiments relate to a semiconductor memory having a plurality of memory blocks.
2. Description of the Related Art
In a semiconductor memory such as a DRAM, a memory cell is coupled to one of a complementary bit line pair via a transfer gate which operates according to the voltage of a word line. In a read operation, data retained in the memory cell is output to one of the bit lines. The other of the bit lines is set to a precharge voltage before the read operation. The voltage difference in the bit line pair is then amplified by a sense amplifier and is output as read data. Generally, while the DRAM is on standby, the bit lines are set to the precharge voltage, and the word line is set to the ground voltage or the like.
For example, when a word line and a bit line short-circuit electrically and a failure occurs, the bad word line is replaced by a redundancy word line. Alternatively, the bad bit line pair is replaced with a redundancy bit line pair. However, the short circuit between the word line and the bit line physically exists even after the failure is relieved. Accordingly, even after the failure is relieved, a leak current flows from a precharge voltage line to the ground line via the short-circuited part. A DRAM having a large leak current is removed as a bad product.
To decrease a standby current failure that accompanies a short failure (hereinafter, also referred to as a cross short failure) between a word line and a bit line, there is proposed a method of coupling a precharge voltage line to bit lines and a sense amplifier in a certain period before a word line is activated (for example, refer to Japanese Laid-open Patent Publication No. H06-52681). In this method, all the bit lines are set to a floating state during a standby period in which an access operation is not performed.
When the semiconductor memory has a plurality of memory blocks, it is preferable that the countermeasure against a failure which sets the bit lines to a floating state during a standby period is implemented only in the memory block where the cross short failure exists. However, there is no technology proposed for detecting the cross short failure and relieving the failure for every memory block in a semiconductor memory having a plurality of memory blocks.